The present disclosure relates generally to semiconductors, and more particularly, to a scribe street structure for backend interconnect semiconductor wafer integration and method for forming the same.
In present metal and dielectric semiconductor wafer integration, during a sawing operation (singulation) of the semiconductor die of a wafer, uncontrollable cracking or chipping occurs within the dielectric layers of the backend interconnect structure of the semiconductor die or within the bulk substrate (Si, etc) of the semiconductor die. Such cracking can propagate into the active die area and cause immediate or latent electrical failure of the device.
One known technique of stopping cracks in a dielectric material includes placing one continuous barrier wall adjacent each chip and a sacrificial composite structure in combination therewith, between the wall and the center of a dicing line. The composite structure includes a means for dispersing the energy associated with crack propagation, whereby any crack having sufficient energy to penetrate the composite structure is transformed into a plurality of weaker cracks incapable of penetrating the barrier wall. However, such a technique has limits with respect to the magnitude of the cracks that it can arrest, and furthermore, does not facilitate a predictable separation path.
In addition, the problem of delamination and crack propagation has historically been solved by a number of methods. One approach included attempting to improve the adhesion strength of the materials being singulated. Another method included constructing a “crack stop” or barrier that impedes crack propagation. Yet another method included increasing the scribe width (i.e., buffer zone) to increase the distance a crack must propagate before it becomes lethal to the device. Still further, another method included reducing the singulation process throughput, either by reducing cut speed or changing saw blades at a more frequent interval. In general, these methods fail to provide for an optimized process.
Accordingly, it would be desirable to provide an improved semiconductor manufacturing method for overcoming the problems in the art.